Digital phase control circuit

ABSTRACT

A digital phase control circuit for the production of a rectangular wave oscillation, synchronized with the aid of data pulses, in which a counter is operative to count pulses of a counter pulse train, counting from a constant initial value to an adjustable final value, with such final value determining the frequency of the rectangular wave oscillation and the final value being adjusted, on the arrival of a data pulse, in dependence upon the contents of the counter, characterized by such counter being in the form of an up-down counter which counts pulses upwardly until a final value is reached and then downwardly to the original initial value, in which the final value is increased or reduced, following the arrival of a data pulse, by a fraction of the final value, while the counter correspondingly counts upwards or downwards, and if the content of the counter is not greater than half the final value, the rectangular wave oscillation being derived at the output of a bistable trigger stage, which is set or reset when the counting content of the counter is correspondingly smaller or greater than half the final value.

United States Patent 1 Kellner et al.

[ DIGITAL PHASE CONTROL CIRCUIT [75] Inventors: Josef Kellner; HansKowalczyk,

both of Germering, Germany [73] Assignee: Siemens Aktiengesellschaft,Berlin & Munich, Germany Primary Examiner-Vincent P. Canney Attorney,Agent, or Firm-Hill, Gross, Simpson, Van

Santen, Steadman, Chiara & Simpson 51 July 1,1975

[ ABSTRACT A digital phase control circuit for the production of arectangular wave oscillation, synchronized with the aid of data pulses,in which a counter is operative to count pulses of a counter pulsetrain, counting from a constant initial value to an adjustable finalvalue, with such final value determining the frequency of therectangular wave oscillation and the final value being adjusted, on thearrival of a data pulse, in dependence upon the contents of the counter,characterized by such counter being in the form of an up-down counterwhich counts pulses upwardly until a final value is reached and thendownwardly to the original initial value, in which the final value isincreased or reduced, following the arrival of a data pulse, by afraction of the final value, while the counter correspondingly countsupwards or downwards, and if the content of the counter is not greaterthan half the final value, the rectangular wave oscillation beingderived at the output of a bistable trigger stage, which is set or resetwhen the counting content of the counter is correspondingly smaller orgreater than half the final value.

21 Claims, 6 Drawing Figures 1 DIGITAL PHASE CONTROL CIRCUIT BACKGROUNDOF THE INVENTION The invention is directed to a digital phase controlcircuit for the production of rectangular wave oscillations,synchronized by means of data pulses, in which a counter is providedwhich counts pulses of a counter pulse train of adjustable frequencyfrom a constant initial value to an adjustable final value, with thefinal value determining the frequency of the rectangular waveoscillation and the final value being set in dependence upon thecontents of the counter at the arrival of the data pulse.

In data transmission from a data transmitter to a data receiver, itfrequently is necessary to produce, in the data receiver, timing pulseswhich are synchronized with data pulses of the data transmitter.Problems here occur that, as a result of variations in parameters withrespect to time in the data transmitter. the data pulses have afrequency which varies relative to time. Further, the data pulses may bereceived only incompletely as a result of interference. Suchinterference may consist of interference pulses occurring between datapulses or that one or more data pulses fail to appear.

An example of a data transmission device which is subject to theabove-mentioned problems is a magnetic tape store for the storage ofbinary signals in which the binary signals are stored in conjunctionwith a selfpulsing recording operation. A conventional, selfpulsingrecording process for magnetic tape stores, currently employed, is thephase encoding recording process in which the binary signals are storedon the magnetic tape as changes in direction of the magnetic flux. Thus,the binary signal 1 is represented by a change from negative to positivemagnetic flux, and the binary signal is represented by an oppositelydirected change. These changes in the magnetic flux representing abinary signal are generally termed bit flux changes. It will beappreciated that with the utilization of flux changes to designate thebinary signals, it is necessary to insert an auxiliary flux changebetween two adjacent bit flux changes when two identical binary signalssuccessively follow one another.

In the read-out of magnetic tape which has been so recorded upon, theread-out signals are induced in a magnetic head, and from such read-outsignals a digitalization circuit derives rectangular data pulses whichare referred to as bit" or auxiliary" pulses in dependence upon whetherthey are produced by bit or auxiliary flux changes.

In order to derive the stored binary signals from the read-out signals,the bit pulses must be separated from the auxiliary pulses, whichoperation is effected by means of a rectangular wave oscillation whichis referred to as "read-out window." The read-out window is always open(binary I) when a bit pulse arrives and is always closed (binary 0)during the period when an auxiliary pulse can arrive.

The recorded binary signals are preceded and followed by synchronizationsignals in order to so set the read-out window that it will alwayspossess a correct phase state and the correct frequency for the read-outof the binary signals.

As the intervals between the data pulses can fluctuate about atheoretical value because of changes in the speed of the magnetic tape,the frequency of the readout window must be constantly matched oradapted to the frequency of the bit pulses. Further, the phase of theread-out window must be so synchronized that the bit pulses occur,insofar as possible. in the center of the open read-out window, and theauxiliary pulses occur, insofar as possible, in the middle of the closedread-out window. Further, changes in the intervals between the datapulses as a result of the auxiliary pulses which occur and displacementsof individual read-out signals through the magnetic properties of themagnetic tape and the magnetic head (peak-shift) must nott be permittedto disturb the synchronization between the data pulses and the read-outwindow. In other words, the read-out window must, even in the case of atemporary drop-out of the data pulses, due to interferernce and thelike, maintain the previously existing frequency to enable thesynchronization to be again continued with correct phase at the end ofthe drop-out period.

Synchronization circuits are already known in the form of controlcircuits which utilize a phase detector and a voltage controlledoscillator which are constructed with components such as employed inanalog circuit technique. A disadvantage of such circuits is thedependence upon component tolerances, environmental conditions andsupply voltages. Further, such circuits frequently have additionaldisadvantages in that they involve components which require adjustmentswhich must be made and often are very difficult to change over to otherdata pulse frequencies.

A phase control circuit has heretofore been proposed which can beexclusively constructed from integrated digital modules and in which thevoltage controlled oscillator is replaced by a first dual counter, whichcounts up from a constant initial value to an adjustable final value ofthe pulses of a counter pulse train of constant frequency, and which issubsequently reset to its initial value. With each resetting a timingpulse is produced and emitted at the output of the phase controlcircuit. The frequency of the timing pulses can be altered by means ofthe final value and is inversely proportional to the final value. Insuch a phase control circuit, the final value is calculated, by means ofa calculating unit, from the contents of the first dual counter upon thearrival of a data pulse, and from the contents of a second dual counterin such manner that the frequency of the timing pulses is, insofar aspossible, equal to the frequency of the data pulses, and that the timingpulses occur, insofar as possible, in the middle of the interval betweenthe data pulses. Such proposed phase control circuit has thedisadvantage that both the bit pulses and the auxiliary pulses areutilized for phase control and thus because of the changing pulseintervals does not have a constant control function. It also has thefurther disadvantage that the final value of the first dual counter isso set that it is proportional to its content on the arrival of a datapulse even when the frequency of the data pulse remains constant andindividual data pulses are displaced by single phase jumps.

SUMMARY OF THE INVENTION The present invention has as its objective toprovide a phase control circuit which has a low degree of sensitivity tonon-recurring phase jumps of individual data pulses.

The desired objective, in a phase control circuit of the type describedis, in accordance with the invention. achieved by the utilization of anup-down counter which is operative to upwardly count until the finalvalue is reached and thereafter counts downward to the initial value,with a control circuit including a device which increases or reduces thefinal value after the arrival of a data pulse, by a fraction of thefinal value at the time when the data pulse arrives, while the countercounts upwards or downwards, and the contents of the counter are nogreater than half the final value. A first bistable trigger stage isprovided which is set or reset when the contents of the counter areeither smaller than or greater than half the final value and whichsupplies the rectangular wave oscillation at its output.

The phase control circuit of the invention has the advantage of a highresistance to faults, as all the pulses, arriving while the contents ofthe counter are greater than halfthe final value, are inactive withrespect to the control function, and as the final value is not setproportional to the contents of the counter upon the arrival of a datapulse, but is adjusted, in each case, by a fraction ofthe stored finalvalue. It also has the further advantage that it can be constructed witha very low cost outlay exclusively from integrated digital modules whichare commercially procurable.

Likewise with suitable design, the final value of the counter may bealtered without the use ofa calculating unit and with a low cost outlayby suitable circuit design, i.e., if the device in the control circuitwhich in creases or reduces the final value contains a final valuecounter which stores the final value, if the final value counter is inthe form of the up-down counter, ifa dif ference counter is included andthe final value is in creased or reduced by a number of counter pulseswhich are applied to a first counter input and a second counter input,respectively, of the final value counter,

and if the difference counter counts off the number of the counterpulses at one of the counter inputs of the final value counter.

A uniform degree of sensitivity, which is independent of the magnitudeof the final value, is achieved if the number of counter pulses atone ofthe counter inputs of the final value counter is equal to a fraction,preferably one sixty-fourth of the final value.

The counting of the counter pulses can be achieved with a relatively lowoutlay, if during each rectangular wave oscillation, the differencecounter is set at a frac tion. preferably one sixty-fourth of the finalvalue and that with each counter pulse supplied to one of the counterinputs of the final value counter. counting is effected downwards to avalue of 0.

If a second bistable trigger stage is provided which is set when thecontents of the counter are equal to the final value and is reset whenthe contents ofthe counter are equal to the initial value, the counterdevice of the counter may be advantageously so switched over that thecounter will count downward and upward when it is correspondingly setand reset.

If only the phase and not the frequency of the rectangular waveoscillation is to be altered when a data pulse arrives displaced by asmall amount from its theoretical time of arrival, it is advantageous toadjust the final value only when a data pulse arrives outside anexpectation period. Such expectation period may be derived with a lowoutlay by providing a comparator which :ompares the contents ofthecounter with a reference value, preferably one thirty secorid of thefinal value and which sets and resets a third bistable trigger stagewhen the contents of the counter become smaller than or greater than therespective reference values.

In order to speed up the control process and to insure the stability ofthe phase control circuit, it is advantageous to reset the counter atits initial value when a data pulse arrives within the expectationperiod and/or to provide, in the control circuit devices which cancelout a change in the final value by means ofa data pulse. when the nextdata pulse to arrive, while the contents of the counter are lower thanhalf the final value, occurs in the expectation period.

In effecting the desired phasing the phase control circuit may berapidly set to the frequency and the phase of the data pulses by theprovision of having the final value counter, during a synchronizationsequence after the arrival of a synchronization pulse, count upward withhalf the counter pulse train frequency until the next synchronizationpulse arrives, and if the counter is set, by means of suchsynchronization pulse, to the initial value.

If, in connection with the recovery of the binary signals stored on amagnetic tape, by means of the phase encoding recording method, thephase control circuit is employed to separate the bit and auxiliarypulses produced by bit and auxiliary flux changes, a constant controlfunction will be achieved by selection of the fre quency of therectangular wave oscillation equal to the frequency of the bit pulsesand with the control circuit containing an AND gate which links the datapulses with the rectangular oscillation and employs, for controlpurposes, the signals at the output ofthe AND gate instead of the datapulses.

BRIEF DESCRIPTION OF THE DRAWINGS in the drawings wherein like referencecharacters indicate like a corresponding parts:

FIG. I shows a chart illustrating the relationships involved in therecording of binary signals on a magnetic tape;

FIG. 2 is a block circuit diagram of a digital phase control circuitemploying the invention;

FIG. 3 is a diagram illustrating various signals of a digital phasecontrol circuit;

FIG. 4 is a schematic diagram, in block form, of a frequency dividercircuit;

FIG. 5 is a schematic diagram, in block form, of a readout windowgenerator; and

FIG. 6 is a schematic diagram, in block form, of a control circuitvDETAIEED DESCRIPTION OF THE INVENTION Referring to the drawings and inparticular to FIG. 1, the line BS represents a plurality of binarysignals 0 or I, recorded on a magnetic tape. In connection with therecording thereof, in accordance with the phase encoding recordingmethod, the binary signals BS are designated by a curve of the magneticflux MP in the longitudinal direction of the magnetic tape asillustrated in FIG. 1 with the length unit s being plotted in theabscissa direction. It will be noted that the spacing between the fluxchanges on the magnetic tape varies in dependence upon the recordedbinary signals BS by a factor of 2, and that an auxiliary flux change isinserted between two adjacent bit flux changes when identical binarysignals follow one another. FIG. 1 also illustrates the read-out signalsLS which are induced in a mag netic head upon readout of the magnetictape which has been recorded upon the above-described manner, with thetime unit t being plotted in the abscissa direction. A digitalizationcircuit is also provided which, at the respective times at which theread-out signals LS exhibit peaks. produces rectangular wave data pulsesDI, which data pulses are assigned to the bit flow changes, and aredesignated as bit pulses, which are represented in FIG. 1 by wide pulseswhile the data pulses DI which are assigned to the auxiliary fluxchanges, referred to as auxiliary pulses, are represented in FIG. I bynarrow pulses.

Also illustrated in FIG. 1 is the read-out window LP by means of whichthe bit pulses are separated from the auxiliary pulses. As will beapparent from a reference to FIG. 1 whenever a data pulse DI arriveswhile the read-out window is open (binary l such pulse is recognized asa bit pulse, and whenever a data pulse DI arrives while the read-outwindow is closed (binary 0), such pulse is recognized as an auxiliarypulse. When the read-out signal LS is positive, the binary signal I isrecognized as the read-out binary signal BL, and whenever the read-outsignal LS is negative, the binary signal 0 is so recognized.

The synchronization signals preceding or following the recorded binarysignals may, for example, comprise a predetermined number of regularlychanging binary signals 1 and 0, and on read-out these synchronizationsignals produce a sequence of synchronization pulses which consists ofbit pulses and contains no auxiliary pulses. In FIG. 1, the first fivebinary signals of the sequence of binary signals BS can be considered tobe synchronization signals.

The circuit diagram of FIG. 2 illustrates, in block form, a digitalphase control circuit utilizing a pulse generator IG, a control circuitRS, a frequency divider FT and a read-out window generator LG. Theread-out window generator LG and the frequency divider FT, takentogether, represent the control path of the phase control circuit. At afirst input the frequency divider FT is supplied with a counter pulsetrain ZT which is produced by the pulse generator IG. The frequencydivider FT is operated to divide the frequency of the counter pulsetrain ZT in accordance with a variable division ratio and contains acounter which by means of the counter pulse trains ZT constantly countup from an initial value of O to an adjustable final value E, at whichthe counter begins to count down to the initial value of 0V The finalvalue E is applied to a second input of the frequency divider FT a phasesignal PS is supplied to a third input of the frequency divider foreffecting a resetting of the counter to 0. The signal ZR appears at theoutput of the frequency divider FT and indicates the counting directionof the counter while the count Z appears at another output of thefrequency divider, which count can be considered as a digitallyrepresented triangular wave oscillation. The final value E can beutilized in adjusting the frequency thereof, and the phase can be variedby resetting the counter by means of the phase signal PS.

Utilizing the count Z and the final value E, the readout windowgenerator LG produces the read-out window LF. The generator LG maycontain a comparator which compares the count Z with half the finalvalue and when the Z is equal to half the final value and the countercounting downward or upward, a bistable trigger stage is set or reset inaccordance therewith. The output signal of the bistable trigger stagerepresents the read-out window LF and possesses the same frequency asthe triangular-shaped oscillation and its phase is displaced in relationto the reversal points of the triangular-shaped oscillation by Theread-out window LF is conducted to the control circuit RS and to adecoder circuit (not illustrated) and by means of the read-out window LFrecovers the recorded binary signals BS from the data pulses DI. Thecontrol circuit RS thus produces the final value E and the phase signalPS in dependence upon the times at which the data pulses DI arrive.Likewise, by means of the final value E and the phase signal PS, thephase and the frequency of the read-out window may be so altered that abit pulse arrives, insofar as possible, in the center of an openread-out window LF and an auxiliary pulse occurs, insofar as possible,in the center of a closed read-out window LF.

If a bit pulse arrives while the counter is counting upwardly, itsignifies that the frequency of the triangular wave oscillation is toogreat and in this case the control circuit RS increases the final valueE and thus causes a reduction in the frequency of the triangular waveoscillation. In like manner, the final value E is correspondinglyreduced if a bit pulse arrives while the counter is counting downwardly.

In addition to the above, an expectation period EB for the bit pulses isproduced in control circuit RS. The employment of an expectation periodEB serves to speed up the control operations. insuring the stability ofthe phase control circuit and rendering the phase control circuitinsensitive to small fluctuations in the bit pulses about theirtheoretical states. Consequently, if a bit pulse arrives within theexpectation period E8, the final value is not altered but only the phasesignal PS is produced. In order to increase the stability. in additionthereto. a previous alteration of the final value E is cancelled outwhen a bit pulse arrives within the expectation period EB.

To prevent auxiliary pulses occurring at irregular intervals fromaffecting the control processes, such pulses are, by means of theread-out window LF, gated out in the control circuit,

FIG. 3 illustrates various signals occurring during the operation of thephase control circuit illustrated in FIG. 2, with the time units t beingplotted in the abscissa direction and the amplitudes of the signalsbeing plotted in the ordinate direction. The count Z is represented by atriangular wave function in analog form. In addition, FIG. 3 alsoillustrates the data pulses DI which are produced in the digitilizationcircuit from the peaks of the read-out signals LS. Again, the bit pulsesare represented by wide pulses while the auxiliary pulses arerepresented by narrow pulses. For the purposes of illustration, it willbe assumed that between the times H and t6, the frequency of the datapulse DI is constant and equal to the nominal frquency and that at thetime 14, a phase jump occurs, while between the times 16 and I7, thefrequency is likewise constant but greater than the nominal frequency.FIG. 3 also illustrates the readout window LF and the expectation periodEB for the bit pulses. Further details of FIG. 3 will be described inconjunction with the circuit diagrams shown in FIGS. 4 to 6,illustrating portions of the digital phase control circuit.

In the exemplary embodiment illustrated in FIG. 4, the frequency dividerFT contains an eight digit dual counter ZA which counts upwards when thecounter pulse trains ZT are present at its input U] and which countsdownward when the counter pulse trains ZT are present at its input D1.The frequency divider also contains an eight digit comparator V] whichcompares the count Z at the output of the counter ZA with the finalvalue E, a bistable trigger stage UD being provided which determineswhether the counter ZA is to count upward or downward and is operativelyconnected to two NAND gates N1 and N2.

The frequency divider FT is supplied with the counter pulse trains ZThaving a constant frequency equal to 256 times the nominal frequency ofthe bit pulses. If the bistable trigger stage UD is set, the counterpulse train ZT is conducted over the NAND gate NZ to the counter inputUI and the counter ZA counts upwards. The final value E, present as adual number at the frequency divider FT, is compared with the count Z,and in the event of identity, the comparitor Vl emits a pulse to thebistable trigger stage UD.

Upon the next counter pulse train ZT, the bistable trigger stage UD isreset and the counter pulse train ZT is now supplied over NAND gate N1to the counter input Dl whereby the counter ZA counts downwards. Whenthe counter reaches the initial value 0, a negative signal 80 is emittedat its output B] which again sets the bistable trigger stage UD, and thecounter ZA again counts upward to the final value E, etc.

it will be noted from the count Z, represented in FIG. 3 in analog form.as a triangular wave oscillation, that the frequency of the triangularwave oscillation is inversely proportional to the size ofthe final valueE. The phase of the triangular wave oscillation is established by meansof the phase signal PS at the reseting input R of the counter ZA, whichsignal sets the counter to the initial value 0.

The read-out window generator LG illustrated in FIG. 5 contains abistable triger stage FE and compara- [or V2 which compares the count Zwith half the final value. As the final value E is in the form ofa dualnum- Jer, it is possible to readily derive the final value, with- )utadditional circuitry outlay, by displacement by one iual position to theright. Upon equality between the :ount Z and half the final value. apulse is emitted from he comparator V2 to two AND gates Al and A2, and fthe identity occurs while the counter ZA is counting lownward, thesignal AB releases the AND gate Al vith such pulse being operable inconjunction with the text counter pulse train ZT to set the bistabletrigger tage FE. On the other hand, if the equality occurs vhile thecounter ZA is counting upwards, the signal \UF releases the AND gate A2and the pulse, in con unction with the next counter pulse train ZTresets the iistable trigger stage FE. The signals AUF and AB thus:orrespond to the signal ZR designating the counting lirection in FIG.2. The read-out window LP is sup ilied at the output of the bistabletrigger stage FE. The ialf final value is illustrated in FIG. 3 as adash-dot line. t will be noted that the read-out window is a binary l .5long as the count Z is lower than the half final value nd is a binary 0as long as the count Z is greater than ialf final value.

in the exemplary embodiment of the control circuit 1S, illustrated inFIG. 6, binary switching elements are mployed in the production of theexpectation period EB and for changing the final value E, and a finalvalue ounter E2 is provided in which the final value E is tored.

The final value counter E2 is set at the frequency of thesynchronization pulses during the sequence of the latter. The frequencyof such pulses can be measured by means of the final value counter EZ bycounting of the number of the counter pulse trains ZT between twosynchronization pulses. As the counter ZA and the frequency divider FTcounts upward and downward between two bit pulses. the final valuecounter EZ need store only half the number of counter pulse trains ZT,and in FIG. 3 it is assumed that synchronization pulses arrive at thetimes [l to !4. Thus at the time 11 the final value counter E2 issupplied with a pulse train ET which is produced from the counter pulsetrains ZT by having the frequency.

The phasing pulse train ET is supplied to the counter input U2 of thefinal value counter EZ over an AND gate A3 of the control circuit R8.The final value counter EZ, like the counter ZA, is an eight digit dualcounter which counts upwards and downwards when pulses are supplied atthe respective counter inputs U2 and D2. The counter EZ counts upwarduntil the time r2 at which the next cynshronization pulse arrives. Atthe same time with the synchronization pulse which arrives at the timeT2, the counter ZA is set, over the reset input R, to the initial value0. The times t] and [2 can be two arbitrary points of time at whichsynchronization pulses arrive. For reasons of security, it isadvantageous to select two synchronization pulses in the middle of thesequence of such pulses.

As the frequency of the counter pulse train ZT is equal to 256 times thenominal frequency of the bit pulses, the final value counter EZ countsup to the final value of 128 as a result of the phasing pulse trains ET.

The counter ZA, after the time 12, is again caused to count upwardly andwhen its count Z is equal to half the final value E/2 64, the bistabletrigger stage FE in the read-out window generator LG is reset and thereadout window LF assumes the binary value 0. The counter ZA counts upto the final value E 128, and then again counts downward. When thedownward count Z is again equal to half the final value E/2 64, thebistable trigger stage FE is again set and the readout window LF assumesthe binary value 7.

Upon arrival of the next synchronization pulse at the time 13. when thecount Z 0, it arrives within the expectation period EB and the phasesignal PS is supplied over a NAND gate N3 to the counter ZA, but as suchcounter already has a count of Z 0, the phase signal PS has noadditional influence. For the production of the final value period EB,the control circuit contains a comparator V3, a bistable trigger stageF5 and two AND gates A5 and A6. The production of the final value periodEB is achieved in a manner similar to that of the read-out window LF,with the comparator V3, however, being supplied with one thirty-secondof the final value E instead of half the final value. For this purpose,the final value E is conducted to the comparator V3 displaced five dualpositions to the right. The ex pectation period E8 is a binary or 2 whenthe counter ZA is respectively smaller than or greater than onethirty-second of the final value. Upon the counter ZA reaching theinitial value of O, the negative signal BO supplies one sixty-fourth ofthe final value to the inputs of the difference counter DZ, whichlikewise is a dual counter.

When the count Z is again equal to one thirty-second of the final value,the expectation period EB becomes a binary O and when the count is againequal to half the final value E/2, the read-out window LF is likewise abinary 0. The counter ZA counts up to the final value E and back downagain to the initial value 0, etc.

It is assumed that at the time [4, as a result of a phase shift, a bitpulse occurs so prematurely that although it arrives within the openread-out window LF, it arrives before the expectation period EB. The bitpulse thereby sets an AND gate A7. a bistable trigger stage F2 and abistable trigger stage F3, the latter stage indicating that the finalvalue E must be reduced as the bit pulse arrived while the counter VAwas counting downward, while the bistable trigger stage F2 is storingthe information that the bit pulse did not arrive during the expectationperiod EB. Upon the setting of the bistable trigger stage F2, a furtherbistable trigger stage F4 is set which stores, until the arrival of thenext bit pulse, the information that the final value counter EZ haspreviously counted downward.

Upon the counter ZA again reaching the count Z=O, one sixty-fourth ofthe final value E is again written into the difference counter DZ and asthe count Z is again greater than half the final value and the read-outwindow LF has assumed a binary value 0, counter pulse trains ZT aresupplied over AND gate A8 and NAND gate N4 to the counter input D2 ofthe final value counter DE and the latter therefore counts downward. Atthe same time, counter pulse trains are also supplied over gate A9 tothe counter input D3 of the difference counter DZ and the latterlikewise counts downward. When the contents of the difference counter is0, there appears at the output B thereof a negative signal which resetsthe bistable trigger stage F3 and thus terminates the downward countingof the difference counter DZ and of the final counter EZ.

As the contents of the difference counter DZ was one sixty-fourth of thefinal value E, the final value counter EZ can at the maximum be reducedby one-fourth of its content. It is of no importance at which count Z ofthe counter ZA between half the value and one thirtysecond of the finalvalue E the bit pulse arrived. In the illustration of FIG. 3, the finalvalue E has been re duced by two counter units.

An auxiliary pulse arrives between the two bit pulses arriving at thetimes [4 and t5. To prevent such auxiliary pulse from affecting thecontrol, it is gated out in an AND gate A4 by means of the read-outwindow LF.

As the frequency of the bit pulses has not changed, the next bit pulsearrives at itd theoretical time t5 and although it arrives within theexpectation period EB, it does not arrive within the count Z=O as thefinal value E has been reduced with the previous bit pulse. The phasesignal PS which resets the counter ZA to O is again supplied over theNAND gate N3. A bistable trigger stage F1 is also set over a NAND gateNS and the bistable trigger stage F2 is reset over an AND gate A10. Thebistable trigger stage Fl supplies counter pulse trains ZT over NANDgate N6 and AND gate A3 to the input U2 of the final value counter EZ,which thus counts upward. In this way the adjustment of the final valuecounter EZ, as the result of the phase jump at the time 4, is cancelledout.

It has been assumed that the frequency of the bit pulses betqeen thetimes 16 and :7 of FIG. 3 is constant and greater than the nominalfrequency. Consequently, the final value E must be reduced with each bitpulse in order to match the frequency of the read-out window LP to thefrequency of the bit pulses. For this purpose the final value E isreduced with each bit pulse in the same manner as described with respectto the phase jump at the time t4.

The final value E is increased correspondingly when the frequency of thebit pulses becomes lower than the nominal frequency. In this case thefinal value E is increased in that the bistable trigger stage Fl.instead of the bistable trigger stage F3 is set, with the bistabletrigger stage F4 being reset. and the counter pulse trains ZT suppliedover the NAND gate N6 and AND gate A3 to the counter input U2 of thefinal value counter EZ.

As a result the final value E is increased or reduced with each bitpulse to effect a matching of the frequency of the readout window LF tothe frequency of the bit pulses. The final value E thus is reduced witheach bit pulse in the same manner as in the case of the phase jump atthe time t4.

The final value E is correspondingly increased when the frequency of thebit pulses becomes lower then the nominal frequency. In this case, thefinal value E is increased as the bistable trigger stage F1 is setinstead of the bistable trigger stage F3, the bistable trigger stage F4is reset and the counter pulse trains ZT are supplied over NAND gate N6and AND gate A3 to the counter input U2 of the final value counter EZ.

It will be appreciated that the frequency of the readout window LF isthus matched to the frequency of the bit pulses irrespective of thechanges that may take place.

lt will be understood that various modifications can be made to thedescribed embodiments without departing from the scope of the presentinvention.

We claim as our Invention:

1. In a digital phase control circuit for the production of arectangular wave oscillation in which synchronization of the rectangularwave oscillation is effected with the aid of data pulses, in which acounter is operative to count pulses of a counter pulse train, countingfrom a constant initial value to an adjustable final value, with suchfinal value determining the frequency of the rectangular waveoscillation and the final value being adjusted on the arrival of a datapulse, in dependence upon the contents of the counter, the combinationof such counter being in the form of an up-down counter which countspulses upwardly until a final value is reached and then downwardly tothe original initial value, a control circuit operatively connected tosaid counter, having means for increasing the final value or reducingthe same, following the arrival of a data pulse, by a fraction of thefinal value, while the counter correspondingly counts upwardly ordownwardly and if the content of the counter is not greater than halfthe final value, and a bistable trigger stage, at the output of whichthe rectangular wave oscillation is derived, operatively connected forseting or resetting when the counting content of the counter iscorrespondingly smaller or greater than half the final value.

2. A digital phase control circuit according to claim 1, wherein saidmeans in the control circuit. which increases or reduces the finalvalue, comprises a final value counter in which the final value isstored, and a difference counter, said final value counter likewisebeing an up-down counter, the final value of which is increased by anumber of counter pulses applied to a first counter input, of such finalvalue counter, or reduced by a number of pulses applied to a secondcounter input thereof the difference counter being connected to countthe number of counter pulses at one of said counter inputs of said finalvalue counter. and operatively connected to selectively end downwardcounting of the final counter.

3. A digital phase control circuit according to claim 2, wherein meansis connected to one of the counter inputs of the final value counteroperative to supply a number of counter pulses thereto with is equal toa fraction, preferably one sixty-fourth of the final value.

4. A digital phase control circuit according to claim 3, wherein saiddifference counter is so constructed that during each rectangular waveoscillation it is set a fraction, preferably one sixty-fourth of thefinal value, and with each counter pulse at one of the counter inputs ofthe final value counter it counts down to O.

5. A digital phase control circuit according to claim 4, comprising infurther combination, a second bistable trigger stage, and means forsetting such stage when the contents of the first-mentioned counter isequal to the final value and for resetting the same when the content ofthe first-mentioned counter is equal to the initial value, toselectively respectively effect a downward or upward counting therein.

6. A digital phase control circuit according to claim 5, comprising infurther connection. means for producing an expectation period, and meansresponsive thereto for adjusting the final value when the data pulsearrives outside such expectation period.

7. A digital phase control circuit according to claim 6, wherein themeans for producing the expectation period comprises a third bistabletrigger stage. and a comparator for comparing the contents for thefirstmentioned counter with a reference value, preferably onethirty-second of the final value, operative to set or reset such thirdbistable a trigger stage when the content of the counter becomes smallerthan or greater respectively than the reference value, the output ofsaid stage determining the expectation period.

8. A digital phase control circuit according to claim 7, comprising infurther combination, means for effecting resetting of the counter to itsinitial value when a data pulse arrives within the expectation period.

9. A digital phase control circuit according to claim 8, comprising infurther combination, means in the control circuit for canceling a changein the final value by a data pulse when the next arriving data pulsearrives in the expectation period while the content of thefirst-mentioned counter is lower than half the final value.

[0. A digital phase control circuit according to claim 9, comprising infurther combination, means operable during a synchronization sequence,after the arrival of a synchronization pulse to effect a counting in thefinal value counter with half the pulse train frequency until the nextsynchronization pulse arrives, and means for setting the first-mentionedcounter, with such synchronization puEse, to the initial value.

11. A digital phase control circuit according to claim 10, for use in amagnetic tape store in which binary sig nals are recorded with the aidof the phase encoding recording method and in which on the read-out of amag netic tape, the bit and auxiliary pulses produced by the bit andauxiliary flux changes are separated from one another, wherein means areprovided for supplying counter pulse trains having a frequency which isso selected that at a given final value, the frequency of therectangular wave oscillation is equal to the frequency of the bitpulses.

12. A digital phase control circuit according to claim ll, comprising inthe control circuit, an AND gate linking the data pulses with therectangular wave oscillation, with the signals at the output of the ANDgate forming control pulses which are fused for the control instead ofthe data pulses.

[3. A digital phase control circuit according to claim 1, comprising infurther combination. a second bistable trigger stage, and means forsetting such stage when the contents of the first-mentioned counter isequal to the final value and for resetting the same when the content ofthe first-mentioned counter is equal to the initial value. toselectively respectively effect a downward or upward counting therein.

14. A digital phase control circuit according to claim 13, comprising infurther combination, means operable during a synchronization sequence,after the arrival of a synchronization pulse to effect a counting in thefinal value counter with half the pulse train frequency until the nextsynchronization pulse arrives, and means for setting the first-mentionedcounter, with such synchronization pulse, to the initial value.

15. A digital phase control circuit according to claim 1, comprising infurther connection, means for producing an expectation period, and meansresponsive thereto for adjusting the final value when the data pulsearrives outside such expectation periodv 16. A digital phase controlcircuit according to claim 15, wherein the means for producing theexpectation period comprises a third bistable trigger stage, and acomparator for comparing the contents for the first mentioned counterwith a reference value, preferably 1/32 of the final value, operative toset or reset such third bistable a trigger stage when the content of thecounter becomes smaller than or greater respectively than the referencevalue, the output of said stage determining the expectation period.

17. A digital phase control circuit according to claim 16, comprising infurther combination, means for effecting resetting of the counter to itsinitial value when a data pulse arrives within the expectation period.

18. A digital phase control circuit according to claim 16, comprising infurther combination, means in the control circuit for canceling in thefinal value by a data pulse when the next arriving data pulse arrives inthe expectation period while the content of the firstmentioned counteris lower than half the final value.

19. A digital phase control circuit according to claim 2, comprising infurther combination, means operable during a synchronization sequence,after the arrival of a synchronization pulse to effect a counting in thefinal value counter with half the pulse train frequency until the nextsynchronization pulse arrives, and means for setting the first-mentionedcounter. with such synchronization pulse, to the initial value.

20. A digital phase control circuit according to claim 1, for use in amagnetic tape store in which binary signals are recorded with the aid ofthe phase encoding recording method and in which on the read-out of amag netic tape, the bit and auxiliary pulses produced by the bit andauxiliary flux changes are separated from one another, wherein means areprovided for supplying counter pulse trains having a frequency which isso selected that at a given final value, the frequency of the LII tionwith the signals at the output of the AND gate forming control pulseswhich are fused for the control instead of the data pulses.

1. In a digital phase control circuit for the production of arectangular wave oscillation in which synchronization of the rectangularwave oscillation is effected with the aid of data pulses, in which acounter is operative to count pulses of a counter pulse train, countingfrom a constant initial value to an adjustable final value, with suchfinal value Determining the frequency of the rectangular waveoscillation and the final value being adjusted on the arrival of a datapulse, in dependence upon the contents of the counter, the combinationof such counter being in the form of an up-down counter which countspulses upwardly until a final value is reached and then downwardly tothe original initial value, a control circuit operatively connected tosaid counter, having means for increasing the final value or reducingthe same, following the arrival of a data pulse, by a fraction of thefinal value, while the counter correspondingly counts upwardly ordownwardly and if the content of the counter is not greater than halfthe final value, and a bistable trigger stage, at the output of whichthe rectangular wave oscillation is derived, operatively connected forseting or resetting when the counting content of the counter iscorrespondingly smaller or greater than half the final value.
 2. Adigital phase control circuit according to claim 1, wherein said meansin the control circuit, which increases or reduces the final value,comprises a final value counter in which the final value is stored, anda difference counter, said final value counter likewise being an up-downcounter, the final value of which is increased by a number of counterpulses applied to a first counter input, of such final value counter, orreduced by a number of pulses applied to a second counter input thereofthe difference counter being connected to count the number of counterpulses at one of said counter inputs of said final value counter, andoperatively connected to selectively end downward counting of the finalcounter.
 3. A digital phase control circuit according to claim 2,wherein means is connected to one of the counter inputs of the finalvalue counter operative to supply a number of counter pulses theretowith is equal to a fraction, preferably one sixty-fourth of the finalvalue.
 4. A digital phase control circuit according to claim 3, whereinsaid difference counter is so constructed that during each rectangularwave oscillation it is set a fraction, preferably one sixty-fourth ofthe final value, and with each counter pulse at one of the counterinputs of the final value counter it counts down to
 0. 5. A digitalphase control circuit according to claim 4, comprising in furthercombination, a second bistable trigger stage, and means for setting suchstage when the contents of the first-mentioned counter is equal to thefinal value and for resetting the same when the content of thefirst-mentioned counter is equal to the initial value, to selectivelyrespectively effect a downward or upward counting therein.
 6. A digitalphase control circuit according to claim 5, comprising in furtherconnection, means for producing an expectation period, and meansresponsive thereto for adjusting the final value when the data pulsearrives outside such expectation period.
 7. A digital phase controlcircuit according to claim 6, wherein the means for producing theexpectation period comprises a third bistable trigger stage, and acomparator for comparing the contents for the first-mentioned counterwith a reference value, preferably one thirty-second of the final value,operative to set or reset such third bistable a trigger stage when thecontent of the counter becomes smaller than or greater respectively thanthe reference value, the output of said stage determining theexpectation period.
 8. A digital phase control circuit according toclaim 7, comprising in further combination, means for effectingresetting of the counter to its initial value when a data pulse arriveswithin the expectation period.
 9. A digital phase control circuitaccording to claim 8, comprising in further combination, means in thecontrol circuit for canceling a change in the final value by a datapulse when the next arriving data pulse arrives in the expectationperiod while the content of the first-mentioned counter is lower thanhalf the final value.
 10. A digiTal phase control circuit according toclaim 9, comprising in further combination, means operable during asynchronization sequence, after the arrival of a synchronization pulseto effect a counting in the final value counter with half the pulsetrain frequency until the next synchronization pulse arrives, and meansfor setting the first-mentioned counter, with such synchronizationpulse, to the initial value.
 11. A digital phase control circuitaccording to claim 10, for use in a magnetic tape store in which binarysignals are recorded with the aid of the phase encoding recording methodand in which on the read-out of a magnetic tape, the bit and auxiliarypulses produced by the bit and auxiliary flux changes are separated fromone another, wherein means are provided for supplying counter pulsetrains having a frequency which is so selected that at a given finalvalue, the frequency of the rectangular wave oscillation is equal to thefrequency of the bit pulses.
 12. A digital phase control circuitaccording to claim 11, comprising in the control circuit, an AND gatelinking the data pulses with the rectangular wave oscillation, with thesignals at the output of the AND gate forming control pulses which arefused for the control instead of the data pulses.
 13. A digital phasecontrol circuit according to claim 1, comprising in further combination,a second bistable trigger stage, and means for setting such stage whenthe contents of the first-mentioned counter is equal to the final valueand for resetting the same when the content of the first-mentionedcounter is equal to the initial value, to selectively respectivelyeffect a downward or upward counting therein.
 14. A digital phasecontrol circuit according to claim 13, comprising in furthercombination, means operable during a synchronization sequence, after thearrival of a synchronization pulse to effect a counting in the finalvalue counter with half the pulse train frequency until the nextsynchronization pulse arrives, and means for setting the first-mentionedcounter, with such synchronization pulse, to the initial value.
 15. Adigital phase control circuit according to claim 1, comprising infurther connection, means for producing an expectation period, and meansresponsive thereto for adjusting the final value when the data pulsearrives outside such expectation period.
 16. A digital phase controlcircuit according to claim 15, wherein the means for producing theexpectation period comprises a third bistable trigger stage, and acomparator for comparing the contents for the first-mentioned counterwith a reference value, preferably 1/32 of the final value, operative toset or reset such third bistable a trigger stage when the content of thecounter becomes smaller than or greater respectively than the referencevalue, the output of said stage determining the expectation period. 17.A digital phase control circuit according to claim 16, comprising infurther combination, means for effecting resetting of the counter to itsinitial value when a data pulse arrives within the expectation period.18. A digital phase control circuit according to claim 16, comprising infurther combination, means in the control circuit for canceling in thefinal value by a data pulse when the next arriving data pulse arrives inthe expectation period while the content of the first-mentioned counteris lower than half the final value.
 19. A digital phase control circuitaccording to claim 2, comprising in further combination, means operableduring a synchronization sequence, after the arrival of asynchronization pulse to effect a counting in the final value counterwith half the pulse train frequency until the next synchronization pulsearrives, and means for setting the first-mentioned counter, with suchsynchronization pulse, to the initial value.
 20. A digital phase controlcircuit according to claim 1, for use in a magnetic tape store in whichbinary signals are recorded with the aid of the phase encoding reCordingmethod and in which on the read-out of a magnetic tape, the bit andauxiliary pulses produced by the bit and auxiliary flux changes areseparated from one another, wherein means are provided for supplyingcounter pulse trains having a frequency which is so selected that at agiven final value, the frequency of the rectangular wave oscillation isequal to the frequency of the bit pulses.
 21. A digital phase controlcircuit according to claim 20, comprising in the control circuit, an ANDgate linking the data pulses with the rectangular wave oscillation, withthe signals at the output of the AND gate forming control pulses whichare fused for the control instead of the data pulses.